# A brief discussion on half adder and full adder

In this particular article Brief discussion on half adder and full adder we are going to discuss half adder, its circuit diagram, its truth table, and circuit diagram using gates. Similarly, we will discuss briefly on Full Adder in easiest way possible.

## Half adder

The simplest combination circuit which performs the arithmetic addition of two binary digits is called a half adder. As shown in fig, the half adder has two inputs and two outputs. The two inputs are the two 1-bit numbers A and B, and the two outputs are the sum (S) of A and B and the carry bit denoted by C. From the truth table of the half adder shown in table, one can understand that the sum output is 1 when either of the inputs (A or B) is 1. And the carry output is 1 when both the inputs (A and B) are 1.

From above table, the logic gate expression for the sum output can be written as a Sum of product expression by summing up the inputs combinations for which the sum is equal to 1.

In the truth table, the sum output is 1 when AB = 01 and AB =10. Therefore, the expression for sum is

S = A‾B + AB‾

Now, this expression can be simplified as

S = A ⊕ B

Similarly, the logic expression for Carry output can be expressed as a sum of product expression by summing up the input combinations for which the Carry is equal to 1. In the truth table, the carry is 1 when AB = 11. Therefore,

C = AB

This expression for C cannot be simplified. The sum output corresponds to a logic Ex-OR function while the carry output corresponds to an AND function. So, the half- adder circuit can be implemented using Ex-OR and AND gates as shown in fig. This fig gives the realisation of the half- adder using minimum number of NAND gates. The implementation of the half -adder circuit using basic gates AND, OR and NOT is shown in fig.

### Full Adder

A half adder has only two inputs and there is no provision to add a carry coming from the lower order bits when multibit addition is performed. For this purpose, a full adder is designed. A full Adder is a combinational circuit that performs the arithmetic sum of three inputs bits and produces a sum output and a carry.

The logic symbol of the full Adder is shown in fig. It consists of three input and two outputs. The two input variables denoted by A (Augend bit) and B (Addend bit) represent the two significant bits to be added. The third input , Cin represents the carry from the previous lower significant position. The outputs are designated by the symbols S (for sum) and Cout (for carry).

#### Truth table for Full Adder

The truth table for the full Adder circuit is shown in fig. The binary variables S given the value of the LSB of the sum, and the binary variable Cout, gives the output carry. A full-adder can be formed using two half-adder circuits and an OR gate as shown in fig.

As shown in table, there are eight possible input combinations for the three inputs and for each case the S and Cout values are listed. From the truth table, the logic expression for S can be written by summing up the input combinations for which the sum output is 1 as:

S = A‾B‾Cin + A‾BCin‾ + AB‾Cin‾ + ABCin

Simplifying the above expression, we get

S = A‾( B‾Cin + BCin‾) + A( B‾Cin‾ + BCin)

S = A‾( B⊕ Cin) + A(B⊕Cin)‾‾

Let B⊕Cin = X

Now, S = A‾X + AX‾ = A⊕X

ReplacingX by B⊕Cin in the above expression, consequently we get

S = A⊕ B⊕ Cin

Similarly, the logic expression for Cout can be written by summing up the input combinations for which Cout is 1, as given below:

Cout = A‾BCin + AB‾Cin + ABCin‾ + ABCin

= BCin (A+A‾) + AB‾Cin + ABCin‾

Hence,

= BCin + AB‾Cin + ABCin‾

Now, the ABCin term is added twice gor simplification.

Cout = BCin + AB‾Cin + ABCin‾ + ABCin + ABCin

And,

= BCin + ACin (B + B‾) + AB (Cin +you Cin‾)

Hence consequently,

= BCin + ACin + AB

From the simplified expression of S and Cout, the full-adder circuit can be implemented using one 3-input Ex-OR gate, three 2-input AND gates and one 3-input OR gate as shown in fig.

##### Conclusion

In this article we have covered all the important information of half and full Adder in detail.