Multiplexer and de-multiplexer theory and circuit diagram

In today’s article Multiplexer and de-multiplexer theory and circuit diagram, we are going to discuss about multiplexer, its truth table, logic or circuit diagram for multiplexer. We will also going to discuss the types or the classification of DUX. We will also going to learn whole concept for de-multiplexer in Detail.

Multiplexer

The term multiplexer means ‘many into one’. Multiplexing is the process of transmitting a number of information over a single line.

A multiplexer is a combination of circuit that select one digital information for several sources. And transmit select information on a single line.

Multiplexer and de-multiplexer theory and circuit diagram

The block diagram multiplexer with n input lime and m select lines and 1 output line. If number of input line is equal to 2ˆn. Selected line are required to select one of the input line.

Classification of multiplexer

1. 4:1 multiplexer:

The logic of 4:1 multiplexer is shown in fig.

In 4:1 multiplexer, there are total four input signal as shown in fig. In figure |D0- D3| shows the four input lines. And it selects |S0- S1|two input lines and hence shows one output line represented by Y.

Data select input (truth table for multiplexer)

In this above table S1 and S2 shows two selected lines. Yinput shows the four data input namely D0, D1, D2 and D3. And Y shows the output line. Here Y0, Y1, Y2 and Y3 are output signals for D0, D1, D2 and D3 input signals.

Expression for output Y

Y can be expressed by adding different output signals for different input signals.

Y = Y0 + Y1 + Y2 + Y3

Logic/ circuit diagram for multiplexer

Explanation- The logic/ circuit diagram for a multiplexer can be explained by using above expression i.e. Y = Y0 + Y1 + Y2 + Y3. In this figure D0, D1, D2 and D3 shows four input signal. S1 and S0 are two selected lines. Here we have used four AND gates to show the expression of Y0, Y1, Y2, and Y3 containing values D0S1‾S0‾, D1S1‾S0, D2S1S0‾ and D3S1S0. Along with that one OR gate is also used.

2. 16:1 multiplexer

A 16 to 1 MUX is shown in fig. It has 16 input namely (D0 – D15) and single output wire and select input (A -D).

Truth table for 16 to 1 MUX is shown below. Here A, B, C and D are selected inputs and Y shows the output.

Expression for Y

Y can be expressed as-

Y = D0‾A‾B‾C‾D‾ + D1‾A‾B‾C‾D + D2‾A‾B‾CD‾ + D3‾A‾B‾CD + D4‾A‾BC‾D‾ + D5‾A‾BC‾D + D6‾A‾BCD‾ + D7‾A‾BCD + D8‾AB‾C‾D‾ + D9‾AB‾C‾D + D10‾AB‾CD‾ + D11‾AB‾CD + D12‾ABC‾D‾ + D13‾ABC‾D + D14‾ABCD‾ + D15‾ABCD

It shows that y generate different signals for different input signals. And consequently resultant Y is combination of all those signals generated by different output.

Logic/circuit diagram for 16 to 1 MUX

Explanation- The logic diagram for 16 to 1 multiplexer is shown in fig. Here we are using 16 AND gates to express Y i.e. D0‾A‾B‾C‾D‾ ,D1‾A‾B‾C‾D , D2‾A‾B‾CD‾ ,  D3‾A‾B‾CD , D4‾A‾BC‾D‾ , D5‾A‾BC‾D , D6‾A‾BCD‾, D7‾A‾BCD,  D8‾AB‾C‾D‾,  D9‾AB‾C‾D , D10‾AB‾CD‾ , D11‾AB‾CD , D12‾ABC‾D‾, D13‾ABC‾D , D14‾ABCD‾ , D15‾ABCD. Along with that we have also used one OR gate to express Y i.e. Y = D0‾A‾B‾C‾D‾ + D1‾A‾B‾C‾D + D2‾A‾B‾CD‾ + D3‾A‾B‾CD + D4‾A‾BC‾D‾ + D5‾A‾BC‾D + D6‾A‾BCD‾ + D7‾A‾BCD + D8‾AB‾C‾D‾ + D9‾AB‾C‾D + D10‾AB‾CD‾ + D11‾AB‾CD + D12‾ABC‾D‾ + D13‾ABC‾D + D14‾ABCD‾ + D15‾ABCD.

De-Multiplexer

D-MUX means one input to many output. D-MUX is process of taking informal one input and transmitting the same over one of the several output.

A D-MUX is a logic circuit that receive information on a single input line and transmit the same information over one of several (2ˆn) output line.

The select input determine to which output the data input will be connected, as the service data change to parallel data. Thus the D-MUX is also called distribute of series to parallel converter.

Classification of D-MUX
(a) 1 to 4 D-MUX

Truth table for 1 to 4 D-MUX

In this table S1 and S0 are called select line. Y0, Y1, Y2 and Y3 are output signals. Y can be expressed as

Y = Y0 + Y1+ Y2 + Y3

And, Y = S1‾S0‾D + S1‾S0D + SS0‾D + S1S0D

Circuit/logic diagram for 1 to 4 D-MUX

A 1:4 D-MUX has a single input D and 4 output (Y0- Y3) and two select line (input)(S1,S0)

It is clear that the data input is connected to the output Y0 when S1= 0 and S0 = 0. And the data input is connected to the output Y1 then S1= 0 and S0= 1 and data input is connected to the output Y2 then S1= 1 and S0= 0.

1:8 D-MUX

Truth table

A 1:8 D-MUX has a single input D and 8 output (Y0-Y7) and three select lines namely S0, S1 and S2.

Circuit/logic diagram for 1 to 8 D-MUX

 

In this particular article we have learn all the basic concepts of multiplexer and de-multiplexer in Detail. We have discussed logic diagram and truth table for different MUX and D-MUX in easiest way possible.

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