Transistor-Transistor Logic (TTL)
The most commonly used saturating logic family called the Transistor-Transistor Logic (TTL), has the fastest switching speed when compared to other logic families that utilize saturated transistor. The series 54/74 TTL family has grown and evolved into five major divisions:
- Standard (SN 54/ 74)
- High-speed (SN54H/ 74H)
- Low-power (SN54L/ 74L)
- Schottky diode clamped (SN54S/ 74S)
- Low power Schottky. (SN54LS/ 74LS)
Although the high speed and low power series were designed for specific applications, all four families are compatible and are capable of interfacing directly with one another.
They have following typical characteristics in common:
- Supply voltage : 0.5V
- Logical 0 output voltage : 0V to 0.4 V
- And Logical 1 output voltage : 2.4V to 5V
- Logical 0 input voltage : 0V to 0.8V
- Logical 1 input voltage : 2V to 5V
- Noise immunity : 0.4V
TTL NAND Gate
The basic circuit for the TTL logic family is the NAND gate. The TTL circuit uses a special single multi-emitter transistor that is fabricated with several emitters at its input. The number of emitters used depends on the desired fan-in of the circuit. Since a multi-emitter transistor is smaller in area than the diodes it replaces, the yield from a wafer is increased. Moreover, smaller area results in lower capacitance to the substrate, thereby reducing the circuit rise. And fall times and hence increasing its speed.
The basic circuit of the TTL NAND gate is shown in fig. The output is taken from the collector of transistor Q4. Each emitter of Q1 acts like a diode. Therefore, transistor Q1 and the 4kΩ resistor act like a 3-input AND gate and the rest of the circuit inverts the signal. Hence, the overall circuit acts like a 3-input NAND gate.
When either or all inputs (A,B and C) are at 0V (logic 0), the corresponding emitter-base junction of Q1 becomes forward biased. The value of R is selected so as to ensure that Q1 is turned ON. However, the value of current iB2 flowing through the base of Q2 reduces the potential at the base of Q2. And hence transistors Q2 and Q4 are cutoff so that the output voltage is at Vcc (logic 1).
If all the inputs are high (logic 1), the emitter-base junction of Q1 is reverse biased so that it has no base current. Hence, Q1 is OFF. However, its collector-base junction is forward-biased supplying base current iB2 to Q2. The current iB2 will be sufficiently large to saturate Q2. As a result, transistor Q2 is turned ON and the drop across R2 is sufficient to forward bias the base-emitter of Q4, thereby turning Q4 ON. Hence, the output at its collector is low (logic 0). The function of diode D is to prevent both Q3 and Q4 from being ON simultaneously.
In the absence of diode D, the transistor Q3 will conduct slightly when the output is LOW. In order to prevent this, the diode is connected between the emitter of Q3. And the collector of Q4. The voltage drop across the diode is connected between the emitter of Q3 and the collector of Q4. The voltage drop across the Diode keeps the base-emitter junction of Q3 reverse-biased. In this way, transistor Q4 only conducts when the output is LOW, which confirms the conditions for NAND operation.
As TTL input circuits require higher drive currents than DTL, they are designed to have high power output stages. The open collector gates are used in three major applications : driving a lamp and relay, performing a wired logic and for the construction of common bus system.
TTL Circuit Output Connections
A number of output connections are provided using TTL logic gates. Each of the five TTL versions comes in one of three output circuit configurations commonly referred to as:
- Totem-Pole output
- Open-collector output
- Tri-state output
In this particular article, we have discussed the transistor-transistor logic TTL, in detail. We have also discussed its different types and properties in easiest way possible.
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